Datasheet

MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2

Freescale Semiconductor 5

Overview

— Programmable highest priority request

— Six groups of interrupts with programmable priority

— External and internal interrupts directed to host processor

— Unique vector number for each interrupt source

• Enhanced secure digital host controller (eSDHC)

— Compatible with the SD Host Controller Standard Specification Version 2.0 with test event

— Compatible with the MMC System Specification Version 4.2

— Compatible with the SD Memory Card Specification Version 2.0 and supports the high capacity

SD memory card

— Compatible with the SD Input/Output (SDIO) Card Specification, Version 2.0

— Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC,

MMCplus, and RS-MMC cards

— Card bus clock frequency up to 33.33 MHz.

— Supports 1-/4-bit SD and SDIO modes, 1-/4-bit modes

– Up to 133 Mbps data transfer for SD/SDIO/MMC cards using 4 parallel data lines

— Supports block sizes of 1 ~ 4096 bytes

• Universal serial bus (USB) dual-role controller

— Designed to comply with Universal Serial Bus Revision 2.0 Specification

— Supports operation as a stand-alone USB host controller

— Supports operation as a stand-alone USB device

— Supports high-speed (480-Mbps), full-speed (12-Mbps), and low-speed (1.5-Mbps) operations.

Low speed is only supported in host mode.

• FlexCAN module

— Full implementation of the CAN protocol specification version 2.0B

— Up to 64 flexible message buffers of zero to eight bytes data length

— Powerful Rx FIFO ID filtering, capable of matching incoming IDs

— Selectable backwards compatibility with previous FlexCAN module version

— Programmable loop-back mode supporting self-test operation

— Global network time, synchronized by a specific message

— Independent of the transmission medium (an external transceiver is required)

— Short latency time due to an arbitration scheme for high-priority messages

• Dual I

C interfaces

— Two-wire interface

— Multiple-master support

— Master or slave I

C mode support

— On-chip digital filtering rejects spikes on the bus

—I

C1 can be used as the boot sequencer