Datasheet

MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
Freescale Semiconductor 53
Package and Pin Listings
Clock Interface
QE_CLK_IN P23 I OV
DD
—
SYS_CLK_IN R23 I OV
DD
—
RTC_PIT_CLOCK V23 I OV
DD
—
Miscellaneous Signals
QUIESCE_B A2 O OV
DD
—
THERM0 D6 I OV
DD
—
GPIO
GPIO[0]/RXCAN1/ SD_CLK/MSRCID0 (DDR ID) E5 IO OV
DD
—
GPIO[1]/TXCAN1/SD_CMD/MSRCID1 (DDR ID) E6 IO OV
DD
—
GPIO[2]/RXCAN2/SD_CD/MSRCID2 (DDR ID) D4 IO OV
DD
—
GPIO[3]/TXCAN2/SD_WP/MSRCID3 (DDR ID) C2 IO OV
DD
—
GPIO[4]/RXCAN3/SD_DAT0/MSRCID4 (DDR ID) C1 IO OV
DD
—
GPIO[5]/TXCAN3/SD_DAT1/MDVAL (DDR ID) B1 IO OV
DD
—
GPIO[6]/RXCAN4/SD_DAT2/QE_EXT_REQ_3 B3 IO OV
DD
—
GPIO[7]/TXCAN4/SD_DAT3/QE_EXT_REQ_1 B2 IO OV
DD
—
USB
USBDR_PWRFAULT/IIC_SDA2/CE_PIO_1 AC4 IO OV
DD
2
USBDR_CLK/UART2_SIN[2]/UART2_CTS_B[1] Y9 I OV
DD
USBDR_DIR/IIC_SCL2 AC3 IO OV
DD
2
USBDR_NXT/UART2_SIN[1]/QE_EXT_REQ_4 AC2 IO OV
DD
—
USBDR_PCTL[0]/UART2_SOUT[1]/
LB_POR_CFG_BOOT_ECC
AB3 IO OV
DD
—
USBDR_PCTL[1]/UART2_SOUT[2]/
UART2_RTS_B1/LB_POR_BOOT_ERR
Y8 O OV
DD
—
USBDR_STP/QE_EXT_REQ_2 W6 IO OV
DD
—
USBDR_TXDRXD[0]/UART1_SOUT[1]/
GPIO[32]/QE_TRB_O
AB7 IO OV
DD
—
USBDR_TXDRXD[1]/UART1_SIN[1]/GPIO[33]/
QE_TRB_I
AB8 IO OV
DD
—
USBDR_TXDRXD[2]/UART1_SOUT[2]/
UART1_RTS_B1/QE_BRG[1]
AC6 IO OV
DD
—
USBDR_TXDRXD[3]/UART1_SIN[2]/
UART1_CTS_B1/QE_BRG[2]
AC5 IO OV
DD
—
USBDR_TXDRXD[4]/GPIO[34]/QE_BRG[3] AB5 IO OV
DD
—
USBDR_TXDRXD[5]/GPIO[35]/QE_BRG[4] Y7 IO OV
DD
—
USBDR_TXDRXD[6]/GPIO[36]/QE_BRG[9] Y6 IO OV
DD
—
Table 52. MPC8306 Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Notes