Datasheet

MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
54 Freescale Semiconductor
Package and Pin Listings
USBDR_TXDRXD[7]/GPIO[37]/QE_BRG[11] Y5 IO OV
DD
—
DUART
UART1_SOUT[1]/LSRCID4/LCS_B[4] C23 O OV
DD
—
UART1_SIN[1]/LDVAL/LCS_B[5] F19 IO OV
DD
—
UART1_SOUT[2]/UART1_RTS_B1/LCS_B[6] D23 O OV
DD
—
UART1_SIN[2]/UART1_CTS_B[1]/LCS_B[7] D22 IO OV
DD
—
Interrupts
IRQ_B0_MCP_IN_B/CE_PI_0 E20 IO OV
DD
—
IRQ_B1/MCP_OUT_B E23 IO OV
DD
—
IRQ_B2/CKSTOP_OUT_B E22 IO OV
DD
—
IRQ_B3/CKSTOP_IN_B F20 I OV
DD
—
I2C / SPI
IIC_SDA1 G20 IO OV
DD
2
IIC_SCL1 J20 IO OV
DD
2
LCLK1/IIC_SCL2/CKSTOP_IN_B H20 IO OV
DD
2
SPISEL_BOOT/IIC_SDA2/CKSTOP_OUT_B F23 O OV
DD
2
SPIMOSI/LSRCID[2] G22 IO OV
DD
—
SPIMISO/LSRCID[3] K20 IO OV
DD
—
SPICLK/LSRCID[0] G23 IO OV
DD
—
SPISEL/LSRCID[1] H22 I OV
DD
—
FEC Management
FEC_MDC H23 O OV
DD
—
FEC_MDIO L20 IO OV
DD
—
FEC1/GTM/GPIO
FEC1_COL/GTM1_TIN[1]/GPIO[16] AB20 IO OV
DD
—
FEC1_CRS/GTM1_TGATE1_B/GPIO[17] AC21 IO OV
DD
—
FEC1_RX_CLK/GPIO[18] Y17 IO OV
DD
—
FEC1_RX_DV/GTM1_TIN[2]/GPIO[19] Y18 IO OV
DD
—
FEC1_RX_ER/GTM1_TGATE[2]_B/GPIO[20] AB19 IO OV
DD
—
FEC1_RXD0/GPIO[21] AC20 IO OV
DD
—
FEC1_RXD1/GTM1_TIN[3]/GPIO[22] AC19 IO OV
DD
—
FEC1_RXD2/GTM1_TGATE[3]_B/GPIO[23] AC18 IO OV
DD
—
FEC1_RXD3/GPIO[24] AB17 IO OV
DD
—
FEC1_TX_CLK/GTM1_TIN4/GPIO[25] Y15 IO OV
DD
—
FEC1_TX_EN/GTM1_TGATE[4]_B/GPIO[26] Y16 IO OV
DD
—
Table 52. MPC8306 Pinout Listing (continued)
Signal Package Pin Number Pin Type Power Supply Notes