Datasheet

MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
58 Freescale Semiconductor
Clocking
22 Clocking
The following figure shows the internal distribution of clocks within the MPC8306.
Figure 42. MPC8306 Clock Subsystem
Figure 43.
The primary clock source for MPC8306 is SYS_CLK_IN.
Core PLL
System
LBC
LCLK[0:1]
core_clk
e300c3 core
csb_clk to rest
csb_clk
Local Bus
Clock
Unit
of the device
lbc_clk
QE PLL
SYS_CLK_IN
Memory
Device
/n
to local bus
Clock
MEMC_MCK
MEMC_MCK
DDR
ddr_clk
DDR
Memory
Device
PLL
to DDR
memory
controller
Clock
/2
Divider
Divider
qe_clk
MPC8306
CLK Gen
QE_CLK_IN
QE Block