Datasheet

MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
Freescale Semiconductor 59
Clocking
22.1 System Clock Domains
As shown in Figure 42, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create four major clock domains:
• The coherent system bus clock (csb_clk)
• The QUICC Engine clock (qe_clk)
• The internal clock for the DDR controller (ddr_clk)
• The internal clock for the local bus controller (lbc_clk)
The csb_clk frequency is derived from the following equation:
csb_clk = SYS_CLK_IN × SPMF Eqn. 1
The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the
csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers
are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is
loaded at power-on reset or by one of the hard-coded reset options. For more information, see the Reset
Configuration chapter in the MPC8306 PowerQUICC II Pro Integrated Communications Processor
Family Reference Manual.
The qe_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF])
and the QUICC Engine PLL division factor (RCWL[CEPDF]) as the following equation:
qe_clk = (QE_CLK_IN × CEPMF)  (1 + CEPDF) Eqn. 2
qe_clk = (QE_CLK_IN × CEPMF)
 (1 + CEPDF) Eqn. 3
For more information, see the QUICC Engine PLL Multiplication Factor section and the “QUICC Engine
PLL Division Factor” section in the MPC8306 PowerQUICC II Pro Integrated Communications
Processor Family Reference Manual for more information.
The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk.
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that
lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the
external local bus clock outputs (LCLK). The LBC clock divider ratio is controlled by LCRR[CLKDIV].
For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8306 PowerQUICC
II Pro Integrated Communications Processor Family Reference Manual.