Datasheet

MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
6 Freescale Semiconductor
Overview
• DMA Engine
— Support for the DMA engine with the following features:
– Sixteen DMA channels
– All data movement via dual-address transfers: read from source, write to destination
– Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations
– Channel activation via one of two methods (for both the methods, one activation per
execution of the minor loop is required):
– Explicit software initiation
– Initiation via a channel-to-channel linking mechanism for continuous transfers
(independent channel linking at end of minor loop and/or major loop)
– Support for fixed-priority and round-robin channel arbitration
– Channel completion reported via optional interrupt requests
— Support for scatter/gather DMA processing
• DUART
— Two 2-wire interfaces (RxD, TxD)
– The same can be configured as one 4-wire interface (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
• Serial peripheral interface (SPI)
— Master or slave support
• Power managemnt controller (PMC)
— Supports core doze/nap/sleep/ power management
— Exits low power state and returns to full-on mode when
– The core internal time base unit invokes a request to exit low power state
– The power management controller detects that the system is not idle and there are
outstanding transactions on the internal bus or an external interrupt.
• Parallel I/O
— General-purpose I/O (GPIO)
– 56 parallel I/O pins multiplexed on various chip interfaces
– Interrupt capability
• System timers
— Periodic interrupt timer
— Software watchdog timer
— Eight general-purpose timers
• Real time clock (RTC) module
— Maintains a one-second count, unique over a period of thousands of years
— Two possible clock sources:
– External RTC clock (RTC_PIT_CLK)
– CSB bus clock
• IEEE Std. 1149.1™ compliant JTAG boundary scan