Datasheet

MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
Freescale Semiconductor 61
Clocking
coherent system bus clock (csb_clk). The following table shows the expected frequency values for the CSB
frequency for selected csb_clk to SYS_CLK_IN ratios.
22.3 Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). The following table shows the encodings for RCWL[COREPLL]. COREPLL
values not listed, and should be considered reserved.
Table 55. System PLL Multiplication Factors
RCWL[SPMF] System PLL Multiplication Factor
0000 Reserved
0001 Reserved
0010 × 2
0011 × 3
0100 × 4
0101 × 5
0110 × 6
0111–1111 Reserved
Table 56. CSB Frequency Options
SPMF csb_clk : sys_clk_in Ratio
SYS_CLK_IN(MHz)
25 33.33 66.67
csb_clk Frequency (MHz)
0010 2:1
133
0011 3:1
0100 4:1 133
0101 5:1
125 167
0110 6:1
Table 57. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio VCO Divider
0-1 2-5 6
nn 0000 n PLL bypassed
(PLL off, csb_clk clocks core directly)
PLL bypassed
(PLL off, csb_clk clocks core directly)
00 0001 0 1:1 2
01 0001 0 1:1 4
10 0001 0 1:1 8
11 0001 0 1:1 8