Datasheet

MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
62 Freescale Semiconductor
Clocking
NOTE
Core VCO frequency = core frequency  VCO divider. The VCO divider
(RCWL[COREPLL[0:1]]), must be set properly so that the core VCO
frequency is in the range of 400–800 MHz.
22.4 QUICC Engine PLL Configuration
The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters. The
following table shows the multiplication factor encodings for the QUICC Engine PLL.
00 0001 1 1.5:1  2
01 0001 1 1.5:1  4
10 0001 1 1.5:1  8
11 0001 1 1.5:1  8
00 0010 0 2:1  2
01 0010 0 2:1  4
10 0010 0 2:1  8
11 0010 0 2:1  8
00 0010 1 2.5:1  2
01 0010 1 2.5:1  4
10 0010 1 2.5:1  8
11 0010 1 2.5:1  8
00 0011 0 3:1  2
01 0011 0 3:1  4
10 0011 0 3:1  8
11 0011 0 3:1  8
Table 58. QUICC Engine PLL Multiplication Factors
RCWL[CEPMF] RCWL[CEPDF]
QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/
(1 + RCWL[CEPDF)
00000–00001 0 Reserved
00010 0  2
00011 0  3
00100 0  4
00101 0  5
00110 0  6
Table 57. e300 Core PLL Configuration (continued)
RCWL[COREPLL]
core_clk : csb_clk Ratio VCO Divider
0-1 2-5 6