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Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-117
Table 16-118 describes the fields of the TMR_ADD register fields for the timer.
16.5.3.10.9 Timer Accumulator Register (TMR_ACC)
Timer accumulator register accumulates the value of the addend register into it. An overflow pulse of the
accumulator is used to increment the timer clock by TMR_CTRL[TCLK_PERIOD]. This register is read
only in normal operation. The register in eTSEC1 is shared for all eTSECs. Figure 16-111 describes the
definition of the TMR_ACC register.
Table 16-119 describes the fields of the TMR_ACC register.
16.5.3.10.10 Timer Prescale Register (TMR_PRSC)
Timer generated output clock prescale register. It is used to adjust output clock frequency that is put onto
the 1588 clock output signal. The register in eTSEC1 is shared for all eTSECs. Figure 16-112 describes
the definition for the TMR_PRSC register.
Table 16-118. TMR_ADD Register Field Descriptions
Bits Name Description
0–31 ADDEND Timer drift compensation addend register value. It is programmed with a value of 2^32/FreqDivRatio.
For example,
TimerOsc = 50 MHz
NominalFreq = 40 MHz
FreqDivRatio = 1.25
ADDEND = ceil(2^32/1.25) = 0xCCCC_CCCD
Offset eTSEC1:0x2_4E24 Access: Read/Write
0 31
R
TMR_ACC
W
Reset All zeros
Figure 16-111. TMR_ACC Register Definition
Table 16-119. TMR_ACC Register Field Descriptions
Bits Name Description
0–31 TMR_ACC 32-bit timer accumulator register
Offset eTSEC1:0x2_4E28 Access: Read/Write
0151631
R
— PRSC_OCK
W
Reset00000000000000000000000000000010
Figure 16-112. TMR_PRSC Register Definition