Information

Enhanced Three-Speed Ethernet Controllers

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

16-122 Freescale Semiconductor

IEEE 802.3z GMII. The RGMII reduces the number of signals required to interconnect the MAC and the

PHY from a maximum of 28 signals (GMII) to 15 signals (GTX_CLK125 included) in a cost effective and

technology independent manner. To accomplish this objective, the data paths and all associated control

signals are multiplexed using both edges of the clock. For gigabit operation, the clocks operate at

125 MHz, and for 10/100 operation, the clocks operate at 2.5 MHz or 25 MHz, respectively. Note that the

GTX_CLK125 input must be provided at 125 MHz for an RGMII interface, regardless of operation speed

(1 Gbps, 100 Mbps, or 10 Mbps). Figure 16-118 depicts the basic components of the gigabit reduced

media-independent interface and the signals required to establish the gigabit Ethernet controllers’ module

connection with a PHY. The RGMII is implemented as defined by the RGMII specification Version 1.2a

9/22/00.

Figure 16-118. eTSEC-RGMII Connection

Transmit Control (TX_EN(TX_EN,TX_ER))

Gigabit Transmit Clock (TSEC

n_GTX_CLK)

Receive Control (RX_DV(RX_DV,RX_ER))

Receive Clock (TSEC

n_RX_CLK)

Management Data I/O

(MDIO)

Management Data Clock

(MDC)

eTSEC

Medium

The management signals (MDC and MDIO) are common to all of the gigabit Ethernet controllers’ module

connections in the system, assuming that each PHY has a different management address.

Gigabit Reference Clock (GTX_CLK125)

Gigabit

PHY

Ethernet

Receive Data (TSEC

_RXD[3:0])

Transmit Data (TSEC

_TXD[3:0])