Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 4-1
Chapter 4
Reset, Clocking, and Initialization
The reset, clocking, and control signals offer many options for operating the device. Various modes and
features can be configured during hard reset or power-on reset. Most configurable features are loaded to
the device through a reset configuration word, and a few device signals are used as reset configuration
inputs during the reset sequence.
4.1 External Signals
The following sections describe the reset and clock signals in detail.
4.1.1 Reset Signals
Table 4-1 describes the reset signals of the device. Section 4.3.2, “Reset Configuration Words,” describes
the signals that also function as reset configuration signals.
Table 4-1. System Control Signals
Signal I/O Description
PORESET I Power-on reset. Initiates the power-on reset flow that resets the device and configures various
attributes of the device, including its clock modes.
State Meaning Asserted—An external agent has triggered a power-on reset sequence.
Negated—No power-on reset.
Timing For timing information, see MPC8308 PowerQUICC II Pro Processor Hardware
Specification.
Reset State Always input.
HRESET
I/O Hard reset. Causes the device to abort all current internal and external transactions and set most
registers to their default values. HRESET
can be asserted completely asynchronously with respect to
all other signals. The device can detect an external assertion of HRESET
while the device is not
asserting hard reset. HRESET is an open-drain signal.
State Meaning Asserted—An external agent or internal hardware has triggered a hard reset. The
internal hardware drives HRESET
until the sequence completes.
Negated—No hard reset.
Timing Assertion—Occur at any time, asynchronously to any clock.
Negation—Must be asserted for at least 32 SYS_CLK_IN cycles.
Requirements An open-drain signal. An external pull-up is required.
Reset State Output, driven low during power-on and hard reset flows. High impedance after reset
flow completes.