Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-161
Table 16-145. Time-Stamp Insertion Programming Requirements
Requirement Behavior if requirement is not met
TMR_CTRL[RTPE]=1 If TMR_CTRL[RTPE]=0, then no time-stamp is
written to a TxPAL.
TxBD[TOE]=1 If TxBD[TOE]=0, then no time-stamp is written
to a TxPAL.
First TxBD[Data Buffer Pointer] is 8-byte aligned The time-stamp will be written to address First
TxBD[Data Buffer Pointer] + 0x10 rounded
down to the nearest 8-byte aligned address,
except at 4K page boundaries, in which case
the time-stamp may be invalid, and the Second
TxBD close status will be lost.
First TxBD[Data Length]=8, 8 bytes for TxFCB If L2 or frame data is included in the Length, the
buffer immediately following the FCB is
transmitted on the line and the frame data
stored in memory will be overwritten with a
time-stamp value after the frame is transmitted.
TxFCB[PTP]=1 If TxBD[PTP]=0, then no time-stamp is written
to a TxPAL.
The TxFCB is followed immediately by a minimum of 16 bytes for the
TxPAL
The time-stamp will be written to address First
TxBD[Data Buffer Pointer] + 0x10.
Second TxBD[Data Buffer Pointers] points to start of L2 or frame data If there is only one TxBD used to transfer a PTP
frame, then no time-stamp is written to a TxPAL.
Second TxBD[Data Length] >= FIFO_TX_THR or includes the entire
frame
If this condition is not true, the time-stamp in
TxPAL is invalid.