Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
4-4 Freescale Semiconductor
4.2.1.2 Reset Actions
The reset control logic determines the cause of reset, synchronizes it if necessary, and resets the
appropriate internal hardware. Each reset flow has a different impact on the device logic:
• Power-on reset has the greatest impact, resetting the entire device, including clock logic and error
capture registers. This does not reset the RTC module. For more information on RTC reset
sequence, see Chapter 15, “Real Time Clock (RTC) Module.”
• Hard reset resets the entire device, excluding RTC module, clock logic, and error capture registers.
The memory controller, system protection logic, interrupt controller, and I/O signals are initialized only
on hard reset. A SRESET causes a high-priority interrupt to the e300 core.
Table 4-4 identifies the reset actions for each reset source.
Checkstop reset If the core enters checkstop state and the checkstop reset is enabled (RMR[CSRE] = 1), the
checkstop reset is asserted. The enabled checkstop event then generates an internal hard reset
sequence.
Software hard reset A hard reset sequence can be initialized by writing to a memory-mapped register (RCR).
Table 4-4. Reset Actions
Action
Reset Source
Power-On Reset
External Hard Reset
Software Watchdog
Bus Monitor
Checkstop
Software Hard Reset
SRESET
Resets:
PLLs, clocks, and error capture registers
Yes No No
Resets:
DDR controller, LBC, I/O multiplexors,
GTM, PIT, GPIO, system configuration,
and local access windows
Yes Ye s N o
Resets other internal logic Yes Ye s N o
Reset configuration words loaded Yes Ye s N o
HRESET
driven by SoC Yes Ye s N o
Hard reset to e300 core Yes Ye s N o
High priority interrupt to the e300 core No No Yes
RTC No No No
Table 4-3. Reset Causes (continued)
Name Description