Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
17-4 Freescale Semiconductor
function is performed on both of these signals with external pull-up resistors. For electrical characteristics,
see MPC8308 PowerQUICC II Pro Processor Hardware Specification.
17.3 Memory Map/Register Definition
Table 17-3 lists the I
2
C–specific registers and their addresses.
Table 17-2. I
2
C Interface Signals—Detailed Signal Descriptions
Signal I/O Description
SCL I/O Serial clock. Performs as an input when the device is programmed as an I
2
C slave. SCL also performs as an
output when the device is programmed as an I
2
C master.
O As outputs for the bidirectional serial clock, these signals operate as described below.
State
Meaning
Asserted/Negated—Driven along with SDAn as the clock for the data.
I As inputs for the bi-directional serial clock, these signals operate as described below.
State
Meaning
Asserted/Negated—The I
2
C unit uses this signal to synchronize incoming data on SDA. The bus
is assumed to be busy when this signal is detected low.
SDA I/O Serial data. Performs as an input when the device is in a receiving mode. SDA also performs as an output
signal when the device is transmitting (as an I
2
C master or a slave).
O As outputs for the bi-directional serial data, these signals operate as described below.
State
Meaning
Asserted/Negated—Data is driven.
I As inputs for the bi-directional serial data, these signals operate as described below.
State
Meaning
Asserted/Negated—Used to receive data from other devices. The bus is assumed to be busy when
SDA is detected low.
Table 17-3. I
2
C Memory Map
Offset I
2
C Register Access Reset Section/Page
I
2
C Controller 1—Block Base Address 0x0_3000
I
2
C Controller 2—Block Base Address 0x0_3100
0x000 I2CADR—I
2
C address register R/W 0x0000 17.3.1.1/17-5
0x004 I2CFDR—I
2
C frequency divider register R/W 0x0000 17.3.1.2/17-5
0x008 I2CCR—I
2
C control register R/W 0x0000 17.3.1.3/17-6
0x00C I2CSR—I
2
C status register R/W 0x0081 17.3.1.4/17-8
0x010 I2CDR—I
2
C data register R/W 0x0000 17.3.1.5/17-9
0x014 I2CDFSRR—I
2
C digital filter sampling rate register R/W 0x0010 17.3.1.6/17-10
0x01C–0x1FF Reserved — — —