Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
17-6 Freescale Semiconductor
controller clock and CSB is 1:1.Clock ratios for I
2
C1 as well as I
2
C2 are not programmable; they are
always 1:1 with CSB. Consider this factor when selecting an FDR value.
17.3.1.3 I
2
C Control Register (I2CCR)
Figure 17-4 shows the I
2
C control register.
Table 17-5. I2C FDR Field Descriptions
Bits Name Description
0–1 — Reserved, should be cleared
2–7 FDR Frequency divider ratio. Used to prescale the clock for bit-rate selection. The serial bit clock frequency of SCL
is equal to the I
2
C controller clock divided by the divider. The serial bit clock frequency divider selections are
described as follows:
FDR
Divider (Decimal)
0x00 384
0x01 416
0x02 480
0x03 576
0x04 640
0x05 704
0x06 832
0x07 1024
0x08 1152
0x09 1280
0x0A 1536
0x0B 1920
0x0C 2304
0x0D 2560
0x0E 3072
0x0F 3840
0x10 4608
0x11 5120
0x12 6144
0x13 7680
0x14 9216
0x15 10240
FDR
Divider (Decimal)
0x16 12288
0x17 15360
0x18 18432
0x19 20480
0x1A 24576
0x1B 30720
0x1C 36864
0x1D 40960
0x1E 49152
0x1F 61440
0x20 256
0x21 288
0x22 320
0x23 352
0x24 384
0x25 448
0x26 512
0x27 576
0x28 640
0x29 768
0x2A 896
FDR
Divider (Decimal)
0x2B 1024
0x2C 1280
0x2D 1536
0x2E 1792
0x2F 2048
0x30 2560
0x31 3072
0x32 3584
0x33 4096
0x34 5120
0x35 6144
0x36 7168
0x37 8192
0x38 10240
0x39 12288
0x3A 14336
0x3B 16384
0x3C 20480
0x3D 24576
0x3E 28672
0x3F 32768
Note: The value’s shown in the table are applicable only for the default value of DFSRR. Refer to AN2919.
Offset 0x0_3008 Access: Mixed
0x0_3108
01234567
R
MEN MIEN MSTA MTX TXAK
—BCST
W RSTA
Reset All zeros
Figure 17-4. I
2
C Control Register (I2CCR)