Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 17-13
• Data transfers in progress are canceled when a STOP condition is detected or if there is a slave
address mismatch. Cancellation of data transactions resets the clock module.
• The bus is detected to be busy upon the detection of a START condition and idle upon the detection
of a STOP condition.
17.4.1.5.2 Control Transfer—Implementation Details
The I
2
C module contains logic that controls the output to the serial data (SDA) and serial clock (SCL) lines
of the I
2
C. The SCL output is pulled low as determined by the internal clock generated in the clock module.
The SDA output can change only at the midpoint of a low cycle of the SCL, unless it is performing a
START, STOP, or repeated START condition. Otherwise, the SDA output is held constant.
SDA is negated when one or more of the following conditions are true:
• Master mode
— Data bit (transmit)
— ACK bit (receive)
— START condition
— STOP condition
— Repeated START condition
• Slave mode
— Acknowledging address match
— Data bit (transmit)
— ACK bit (receive)
The SCL signal corresponds to the internal SCL signal when one or more of the following conditions are
true in either master or slave mode:
• Master mode
— Bus owner
— Lost arbitration
— START condition
— STOP condition
— Repeated START condition begin
— Repeated START condition end
• Slave mode
— Address cycle
— Transmit cycle
— ACK cycle