Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
17-22 Freescale Semiconductor
It is recommended that a sync instruction follow each I
2
C register read or write to guarantee that register
accesses occur in order.
Figure 17-11. Example I
2
C Interrupt Service Routine Flowchart
Clear I2CSR[MIF]
I2CCR[MSTA]
== 0== 1
I2CSR[MAL]
I2CCR[MTX]
== 1
== 1
== 0
Clear I2CSR[MAL]
EOI
I2CSR[MAAS]
I2CSR[SRW]
Set I2CCR[MTX]
== 0
Clear I2CCR[MTX]
Write I2CDR
dummy read
EOI
== 1
Slave Addr. Phase
Slave Data Cycle
I2CCR[MTX]
== 1
== 0
Slave Xmit
I2CSR[RXAK]
== 1
== 0
Write next byte
to I2CDR
EOI
Slave Received
Read I2CDR
and store
All done
Y
N
Set I2CCR[TXAK]
Read I2CDR
(dummy read)
Y
N
Last byte
Next-to-last
Generate
Read I2CDR
and store
EOI
Y
N
Set
Master Rcv
STOP
I2CCR[TXAK]
byte
Last byte
YN
I2CSR[RXAK]
== 1
Write next byte
to I2CDR
== 0
EOI
Generate
Master Xmit
STOP
B
== 0
== 1
A
== 0
A
B
I2CSR[MAAS]
B
== 0
== 1
Clear I2CCR[MTX]
End of address phase for
master receive mode?
N
Only one byte
to receive?
Y
Y
Set
I2CCR[TXAK]
Read I2CDR
(dummy read)
Clear I2CCR[MTX]
N