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MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 18-1
Chapter 18
DUART
This chapter describes the two (dual) universal asynchronous receiver/transmitters (UARTs) of the device.
It describes the functional operation, the DUART initialization sequence, and the programming details for
the DUART registers and features.
18.1 Overview
The DUART consists of two (dual) universal asynchronous receiver/transmitters (UARTs). The UARTs
act independently; all references to UART refer to one of these receiver/transmitters. Each UART is
clocked by the system clock. The DUART programming model is compatible with the PC16552D.
The UART interface is point-to-point, meaning that only two UART devices are attached to the connecting
signals. As shown in Figure 18-1, each UART module consists of the following:
• Receive and transmit buffers
• 16-bit counter for baud rate generation
• Interrupt control logic
Figure 18-1. UART Block Diagram
Receive Buffer
UART Module Internal Bus
Address Bus
Control
Data
16-Bit Counter/
Baud Rate Generator
SIN
SOUT
Interrupt
Control
Logic
Control
Transmit Buffer
system _clk
HRESET
int