Information

DUART
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 18-5
18.3.1 Register Descriptions
The following sections describe the UART1 and UART2 registers.
18.3.1.1 Receiver Buffer Registers (URBR1 and URBR2)
These registers contain the data received from the transmitter on the UART buses. In FIFO mode, when
read, they return the first byte received. For FIFO status information, refer to the UDSR[RXRDY]
description.
Except for the case when there is an overrun, URBR returns the data in the order it was received from the
transmitter. Refer to the ULSR[OE] description, Section 18.3.1.9, “Line Status Registers (ULSR1 and
ULSR2).” Figure 18-2 shows the receiver buffer registers. Note that these registers have same offset as the
UTHRs.
Table 18-4 describes URBR.
18.3.1.2 Transmitter Holding Registers (UTHR1 and UTHR2)
A write to these 8-bit registers causes the UART devices to transfer 5 to 8 data bits on the UART bus in
the format set up in the ULCR (line control register). In FIFO mode, data written to UTHR is placed into
the FIFO. The data written to UTHR is the data sent onto the UART bus, and the first byte written to UTHR
is the first byte onto the bus. UDSR[TXRDY] indicates when the FIFO is full. Refer to Table 18-20 and
Table 18-21.
0x0_4607 USCR—ULCR[DLAB] = x UART2 scratch register R/W 0x0000 18.3.1.10/18-14
0x0_4610 UDSR—ULCR[DLAB] = x UART2 DMA status register R 0x0001 18.3.1.12/18-15
Offset: 0x0_4500, 0x0_4600 Access: User read-only
0 7
R DATA
W
Reset All zeros
Figure 18-2. Receiver Buffer Registers (URBR1 and URBR2)
Table 18-4. URBR Field Descriptions
Bits Name Description
0–7 DATA Data received from the transmitter on the UART bus [read only]
Table 18-3. DUART Register Summary (continued)
Offset Register Access Reset Section/Page