Information

DUART
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
18-8 Freescale Semiconductor
Figure 18-6 shows the bits in the UIER.
Table 18-9 describes the UIER fields.
18.3.1.5 Interrupt ID Registers (UIIR1 and UIIR2)
The UIIRs indicate when an interrupt is pending from the corresponding UART and what type of interrupt
is active. They also indicate if the FIFOs are enabled.
The DUART prioritizes interrupts into four levels and records these in the corresponding UIIR. The four
levels of interrupt conditions in order of priority are as follows:
1. Receiver line status
2. Received data ready/character time-out
3. Transmitter holding register empty
4. MODEM status
See Table 18-11 for more details.
When the UIIR is read, the associated DUART serial channel freezes all interrupts and indicates the
highest priority pending interrupt. While this read transaction is occurring, the associated DUART serial
channel records new interrupts, but does not change the contents of UIIR until the read access is complete.
Offset: 0x0_4501, 0x0_4601 Access: User read/write
0 34567
R
— EMSI ERLSI ETHREI ERDAI
W
Reset All zeros
Figure 18-6. Interrupt Enable Registers (UIER1 and UIER2)
Table 18-9. UIER Field Descriptions
Bits Name Description
0–3 — Reserved
4 EMSI Enable MODEM status interrupt
0 Mask interrupts caused by UMSR[DCTS] being set.
1 Enable and assert interrupts when UMSR[CTS] changes state.
5 ERLSI Enable receiver line status interrupt
0 Mask interrupts when ULSR’s overrun, parity error, framing error, or break interrupt bits are set.
1 Enable and assert interrupts when ULSR’s overrun, parity error, framing error or break interrupt bits are
set.
6 ETHREI Enable transmitter holding register empty interrupt
0 Mask interrupt when ULSR[THRE] is set.
1 Enable and assert interrupts when ULSR[THRE] is set.
7 ERDAI Enable received data available interrupt
0 Mask interrupt when new receive data is available or receive data time-out has occurred.
1 Enable and assert interrupts when a new data character is received from the external device and/or a
time-out interrupt occurs in FIFO mode.