Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 19-1
Chapter 19
Serial Peripheral Interface
19.1 Overview
The serial peripheral interface (SPI) allows the device to exchange data between other PowerQUICC
family chips, the MC68360, MC68302, M68HC11, and M68HC05 microcontroller families, and other
family devices. The SPI can be used to communicate with peripheral devices such as EEPROMs, real-time
clocks, A/D converters, and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface
(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an
independent baud-rate generator, and a control unit. The transmitter and receiver sections use the same
clock, which is derived from the SPI baud rate generator in master mode or externally in slave mode.
During an SPI transfer, data is sent and received simultaneously.
The SPI receiver and transmitter are double-buffered, as shown in the block diagram in Figure 19-1. This
gives an effective FIFO size (latency) of 2 characters. The SPI’s MSB/LSB is shifted out first. When the
SPI is disabled in the SPI mode register (SPMODE[EN] = 0), it consumes little power.
Figure 19-1. SPI Block Diagram
SPI Mode Register Transmit_Register Receive_Register
Counter
Shift_Register
SPI Baud Rate Generator
Signal Interface
SPI Block
SPIMOSISPISEL SPIMISO SPICLK
TxDRxD IN_CLK
Peripheral Bus
Transmit_Buffer Receive_Buffer
Input Clock