Information

Serial Peripheral Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
19-6 Freescale Semiconductor
19.2 External Signal Descriptions
The SPI’s four wire interface consists of transmit, receive, clock, and slave select.
19.2.1 Overview
Table 19-1 lists signal properties.
19.2.2 Detailed Signal Descriptions
Table 19-2 describes the signals in detail.
Table 19-1. Signal Properties
Name Function Reset Pull Up
SPIMISO Master input slave output — Required in open drain mode
SPIMOSI Master output slave input — Required in open drain mode
SPICLK Input/output serial clock connected to the other SPICLK — Required in open drain mode
SPISEL
SPI slave select — Required in open drain mode
Table 19-2. Detailed Signal Descriptions
Signal I/O Description
SPIMISO I/O Master input slave output
State
Meaning
Asserted—The data that has been transmitted/received from/to the SPI (depends if master or
slave mode) is high
Negated—The data that has ben transmitted/received from/to the SPI (depends if master or
slave mode) is low
Timing Assertion—According to the SPICLK assertion/negation/in the middle of phase (depends on
SPMODE)
Negation—According to the SPICLK assertion/negation/in the middle of phase (depends on
SPMODE)
SPIMOSI I/O Master output slave input
State
Meaning
Asserted—The data that has been transmitted/received from/to the SPI (depends if master or
slave mode) is high
Negated—The data that has ben transmitted/received from/to the SPI (depends if master or
slave mode) is low
Timing Assertion—According to the SPICLK assertion/negation/in the middle of phase (depends on
SPMODE)
Negation—According to the SPICLK assertion/negation/in the middle of phase (depends on
SPMODE)