Information

Serial Peripheral Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 19-7
The SPI can be configured as a slave or a master in single- or multiple-master environments mode. The
master SPI generates the transfer clock SPICLK using the SPI baud rate generator (BRG).The SPI BRG
takes its input from input clock, which is generated in the device clock synthesizer.
SPICLK is a gated clock, active only during data transfers. Four combinations of SPICLK phase and
polarity can be configured with the clock invert (SPMODE[CI]) and clock phase (SPMODE[CP]) register
bits. SPI signals can also be configured as open-drain to support a multiple-master configuration in which
a shared SPI signal is driven by the device or an external SPI device.
The SPI master-in slave-out SPIMISO signal acts as an input for master devices and as an output for slave
devices. Conversely, the master-out slave-in SPIMOSI signal is an output for master devices and an input
for slave devices. The dual functionality of these signals allows the SPIs in a multiple-master environment
to communicate with one another using a common hardware configuration.
• When the SPI is a master, SPICLK is the clock output signal that shifts received data in from
SPIMISO and transmitted data out to SPIMOSI. SPI masters must output a slave select signal to
enable SPI slave devices using a separate general-purpose I/O signal. Assertion of the SPISEL
while the SPI is configured as a master causes an error.
• When the SPI is a slave, SPICLK is the clock input that shifts received data in from SPIMOSI and
transmitted data out through SPIMISO. SPISEL is the enable input to the SPI slave. In a
multiple-master environment, SPISEL (always an input) is also used to detect an error when more
than one master is operating.
19.3 Memory Map/Register Definition
Table 19-3 shows the memory mapped registers of the SPI and their offsets. It lists the offset, name, and a
cross-reference to the complete description of each register. Note that the full register address is comprised
SPICLK I/O Serial clock in or serial clock out for slave or master mode respectively
State
Meaning
Assertion/Negation according to SPMODE[PM,DIV16] register rate configuration
Timing Assertion/Negation—during frame reception/transmission
SPISEL
I SPI slave select
State
Meaning
Asserted—In slave mode declares the slave has been selected for the coming frame.
In master mode assertion causes MME multiple-master error.
Negated—In slave mode means the specific SPI has not been selected.
In master mode needs to be negated for regular operation.
Timing Assertion—In slave mode along with the data from the slave
Negation—In slave mode with the end of the frame (according to SPMODE[LEN]).
In master mode before data is first written to SPITD and remains constant.
Table 19-2. Detailed Signal Descriptions (continued)
Signal I/O Description