Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor A-3
A.3 Watchdog Timer (WDT)
A.4 Real Time Clock (RTC)
A.5 Periodic Interval Timer (PIT)
Table A-3. Watchdog Timer (WDT) Registers
Watchdog Timer (WDT)—Block Base Address 0x0_0200
Offset Register Access Reset Section/Page
0x000–0x003 Reserved — — —
0x004 System watchdog control register (SWCRR) R/W 0xFFFF_0003
or
0xFFFF_0007
1
1
SWCRR[SWEN] reset value directly depends on RCWHR[SWEN] (reset configuration word high).
5.3.4.1/5-34
0x008 System watchdog count register (SWCNR) R 0x0000_FFFF 5.3.4.2/5-35
0x00C–0x00D Reserved — — —
0x00E System watchdog service register (SWSRR) R/W 0x0000 5.3.4.3/5-36
Table A-4. Real Time Clock (RTC) Registers
Offset Register Access Reset Value
1
1
It refers to the case where software writes to a specific RTC register, RTCCR. For more information, see Section 15.8.1.1,
“RTC Reset Sequence.”
Section/Page
Real Time Clock (RTC)—Block Base Address 0x0_0300
0x000 Real time counter control register (RTCNR) R/W 0x0000_0000 15.6.1/15-6
0x004 Real time counter load register (RTLDR) R/W 0x0000_0000 15.6.2/15-7
0x008 Real time counter prescale register (RTPSR) R/W 0x0000_0000 15.6.3/15-7
0x00C Real time counter register (RTCTR) R 0x0000_0000 15.6.4/15-8
0x010 Real time counter event register (RTEVR) w1c 0x0000_0000 15.6.5/15-8
0x014 Real time counter alarm register (RTALR) R/W 0xFFFF_FFFF 15.6.6/15-9
0x018–0x01F Reserved — —
Table A-5. Periodic Interval Timer (PIT) Registers
Periodic Interval Timer (PIT)—Block Base Address 0x0_0400
Offset Register Access Reset Section/Page
0x000 Periodic interval timer control register (PTCNR) R/W 0x0000_0000 5.5.5.1/5-49
0x004 Periodic interval timer load register (PTLDR) R/W 0x0000_0000 5.5.5.2/5-50
0x008 Periodic interval timer prescale register (PTPSR) R/W 0x0000_0000 5.5.5.3/5-50
0x00C Periodic interval timer counter register (PTCTR) R 0x0000_0000 5.5.5.4/5-51