Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
A-12 Freescale Semiconductor
A.17 Serial Peripheral Interface (SPI)
0x0C4 LTECCR—Transfer error ECC register w1c 0x0000_0000 10.3.1.14/10-29
0x0C8–
0x0CC
Reserved — — —
0x0D0 LBCR—Configuration register R/W 0x0004_0000 10.3.1.15/10-30
0x0D4 LCRR—Clock ratio register R/W 0x8000_0008 10.3.1.16/10-31
0x0D8–
0x0DC
Reserved — — —
0x0E0 FMR—Flash mode register R/W 0x0000_0n00 10.3.1.17/10-32
0x0E4 FIR—Flash instruction register R/W 0x0000_0000 10.3.1.18/10-34
0x0E8 FCR—Flash command register R/W 0x0000_0000 10.3.1.19/10-35
0x0EC FBAR—Flash block address register R/W 0x0000_0000 10.3.1.20/10-36
0x0F0 FPAR—Flash page address register R/W 0x0000_0000 10.3.1.21/10-36
0x0F4 FBCR—Flash byte count register R/W 0x0000_0000 10.3.1.22/10-38
0x0F8–
0x0FC
Reserved — — —
0x100 FECC0—Flash ECC block 0 register R 0x0000_0000 10.3.1.23/10-38
0x104 FECC1—Flash ECC block 1 register R 0x0000_0000 10.3.1.23/10-38
0x108 FECC2—Flash ECC block 2 register R 0x0000_0000 10.3.1.23/10-38
0x10C FECC3—Flash ECC block 3 register R 0x0000_0000 10.3.1.23/10-38
Table A-17. Serial Peripheral Interface (SPI) Registers
Serial Peripheral Interface (SPI)—Block Base Address 0x0_7000
Offset Register Access Reset Section/Page
0x000–0x01F Reserved — — —
0x020 SPI mode register (SPMODE) R/W 0x0000_0000 19.3.1.1/19-8
0x024 SPI event register (SPIE) Mixed 0x0000_0000 19.3.1.2/19-10
0x028 SPI mask register (SPIM) R/W 0x0000_0000 19.3.1.3/19-11
0x02C SPI command register (SPCOM) W 0x0000_0000 19.3.1.4/19-13
0x030 SPI transmit register (SPITD) W 0x0000_0000 19.3.1.5/19-13
0x034 SPI receive register (SPIRD) R 0xFFFF_FFFF 19.3.1.6/19-14
0x038–0xFFF Reserved — — —
Table A-16. Enhanced Local Bus Controller Registers (continued)
Enhanced Local Bus Controller—Block Base Address 0x0_5000
Offset Register Access Reset Section/Page