Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor A-19
0xBE4 CSB System Write DMA Interrupt Enable Register
(PEX_CSWDIER)
R/W 0x0000_0000 14.5.8.2/14-95
0xBE8 CSB System Read DMA Interrupt Enable Register
(PEX_CSRDIER)
R/W 0x0000_0000 14.5.8.3/14-96
0xBEC CSB System Miscellaneous Interrupt Enable Register
(PEX_CSMIER)
R/W 0x0000_0002 14.5.8.4/14-97
0xBF0 CSB System PIO Interrupt Status Register (PEX_CSPISR) w1c 0x0000_0000 14.5.8.5/14-99
0xBF4 CSB System Write DMA Interrupt Status Register
(PEX_CSWDISR)
w1c 0x0000_0000 14.5.8.6/14-100
0xBF8 CSB System Read DMA Interrupt Status Register
(PEX_CSRDISR)
w1c 0x0000_0000 14.5.8.7/14-100
0xBFC CSB System Miscellaneous Interrupt Status Register
(PEX_CSMISR)
w1c 0x0000_0000 14.5.8.8/14-101
Power Management Registers
0xC80 PCI Express PM Control Register (PEX_PM_CTRL) R/W 0x0000_0000 14.5.9.1/14-103
PCI Express Outbound Address Mapping Registers
0xCA0 PCI Express Outbound Window Attributes Register 0
(PEX_OWAR0)
R/W 0x0000_0000 14.5.10.1/14-104
0xCA4 PCI Express Outbound Window Base Address Register 0
(PEX_OWBAR0)
R/W 0x0000_0000 14.5.10.2/14-105
0xCA8 PCI Express Outbound Window Translation Address Register
Low 0 (PEX_OWTARL0)
R/W 0x0000_0000 14.5.10.3/14-106
0xCAC PCI Express Outbound Window Translation Address Register
High 0 (PEX_OWTARH0)
R/W 0x0000_0000 14.5.10.4/14-106
0xCB0 PCI Express Outbound Window Attributes Register 1
(PEX_OWAR1)
R/W 0x0000_0000 14.5.10.1/14-104
0xCB4 PCI Express Outbound Window Base Address Register 1
(PEX_OWBAR1)
R/W 0x0000_0000 14.5.10.2/14-105
0xCB8 PCI Express Outbound Window Translation Address Register
Low 1 (PEX_OWTARL1)
R/W 0x0000_0000 14.5.10.3/14-106
0xCBC PCI Express Outbound Window Translation Address Register
High 1 (PEX_OWTARH1)
R/W 0x0000_0000 14.5.10.4/14-106
0xCC0 PCI Express Outbound Window Attributes Register 2
(PEX_OWAR2)
R/W 0x0000_0000 14.5.10.1/14-104
0xCC4 PCI Express Outbound Window Base Address Register 2
(PEX_OWBAR2)
R/W 0x0000_0000 14.5.10.2/14-105
0xCC8 PCI Express Outbound Window Translation Address Register
Low 2 (PEX_OWTARL2)
R/W 0x0000_0000 14.5.10.3/14-106
0xCCC PCI Express Outbound Window Translation Address Register
High 2 (PEX_OWTARH2)
R/W 0x0000_0000 14.5.10.4/14-106
Table A-20. PCI Express Controller Registers
PCI Express—Block Base Address 0x0_9000
Offset Register Access Reset Section/Page