Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor A-21
A.20 Enhanced Three-Speed Ethernet Controllers (eTSECs)
0xE8C PCI Express RC Inbound Window Base Address Register High
2 (PEX_RCIWBARH2)
R/W 0x0000_0000 14.5.12.4/14-111
0xE90 PCI Express RC Inbound Window Attributes Register 3
(PEX_RCIWAR3)
R/W 0x0000_0000 14.5.12.1/14-109
0xE94 PCI Express RC Inbound Window Translation Address Register
3 (PEX_RCIWTAR3)
R/W 0x0000_0000 14.5.12.2/14-110
0xE98 PCI Express RC Inbound Window Base Address Register Low 3
(PEX_RCIWBARL3)
R/W 0x0000_0000 14.5.12.3/14-110
0xE9C PCI Express RC Inbound Window Base Address Register High
3 (PEX_RCIWBARH3)
R/W 0x0000_0000 14.5.12.4/14-111
1
MPC8308 does not support these registers in accordance with the PCIe specification. For more information, see PCI Express
Base Specification, March 28, 2005 (Page 357-358). These registers are mentioned here only for completeness. It is
recommended not to change the reset values of these registers.
Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers
eTSEC 1—Block Base Address 0x2_4000
eTSEC 2—Block Base Address 0x2_5000
eTSEC1
Offset
Name
1
Access
2
Reset Section/Page
eTSEC General Control and Status Registers
0x000 TSEC_ID*—Controller ID register R 0x0124_0106 16.5.3.1.1/16-21
0x004 TSEC_ID2*—Controller ID register R 0x0030_00F0 16.5.3.1.2/16-22
0x008–
0x00C
Reserved — — —
0x010 IEVENT—Interrupt event register w1c 0x0000_0000 16.5.3.1.3/16-22
0x014 IMASK—Interrupt mask register R/W 0x0000_0000 16.5.3.1.4/16-26
0x018 EDIS—Error disabled register R/W 0x0000_0000 16.5.3.1.5/16-28
0x01C Reserved — — —
0x020 ECNTRL—Ethernet control register R/W 0x0000_0000 16.5.3.1.6/16-30
0x024 Reserved — — —
0x028 PTV—Pause time value register R/W 0x0000_0000 16.5.3.1.7/16-31
0x02C DMACTRL—DMA control register R/W 0x0000_0000 16.5.3.1.8/16-32
0x030 TBIPA—TBI PHY address register R/W 0x0000_0000 16.5.3.1.9/16-33
0x034–
0x0FC
Reserved — — —
eTSEC Transmit Control and Status Registers
Table A-20. PCI Express Controller Registers
PCI Express—Block Base Address 0x0_9000
Offset Register Access Reset Section/Page