Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
A-22 Freescale Semiconductor
0x100 TCTRL—Transmit control register R/W 0x0000_0000 16.5.3.2.1/16-34
0x104 TSTAT—Transmit status register w1c 0x0000_0000 16.5.3.2.2/16-36
0x108 DFVLAN*—Default VLAN control word R/W 0x8100_0000 16.5.3.2.3/16-40
0x10C Reserved — — —
0x110 TXIC—Transmit interrupt coalescing register R/W 0x0000_0000 16.5.3.2.4/16-41
0x114 TQUEUE*—Transmit queue control register R/W 0x0000_8000 16.5.3.2.5/16-42
0x118–
0x13C
Reserved — — —
0x140 TR03WT*—TxBD Rings 0–3 round-robin weightings R/W 0x0000_0000 16.5.3.2.6/16-42
0x144 TR47WT*—TxBD Rings 4–7 round-robin weightings R/W 0x0000_0000 16.5.3.2.7/16-43
0x148–
0x180
Reserved — — —
0x184 TBPTR0—TxBD pointer for ring 0 R/W 0x0000_0000 16.5.3.2.8/16-44
0x188 Reserved — — —
0x18C TBPTR1*—TxBD pointer for ring 1 R/W 0x0000_0000 16.5.3.2.8/16-44
0x190 Reserved — — —
0x194 TBPTR2*—TxBD pointer for ring 2 R/W 0x0000_0000 16.5.3.2.8/16-44
0x198 Reserved — — —
0x19C TBPTR3*—TxBD pointer for ring 3 R/W 0x0000_0000 16.5.3.2.8/16-44
0x1A0 Reserved — — —
0x1A4 TBPTR4*—TxBD pointer for ring 4 R/W 0x0000_0000 16.5.3.2.8/16-44
0x1A8 Reserved — — —
0x1AC TBPTR5*—TxBD pointer for ring 5 R/W 0x0000_0000 16.5.3.2.8/16-44
0x1B0 Reserved — — —
0x1B4 TBPTR6*—TxBD pointer for ring 6 R/W 0x0000_0000 16.5.3.2.8/16-44
0x1B8 Reserved — — —
0x1BC TBPTR7*—TxBD pointer for ring 7 R/W 0x0000_0000 16.5.3.2.8/16-44
0x1C0–
0x200
Reserved — — —
0x204 TBASE0—TxBD base address of ring 0 R/W 0x0000_0000 16.5.3.2.9/16-45
0x208 Reserved — — —
0x20C TBASE1*—TxBD base address of ring 1 R/W 0x0000_0000 16.5.3.2.9/16-45
0x210 Reserved — — —
Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers (continued)
eTSEC 1—Block Base Address 0x2_4000
eTSEC 2—Block Base Address 0x2_5000
eTSEC1
Offset
Name
1
Access
2
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