Information

Complete List of Configuration, Control, and Status Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor A-31
A.21 SerDes PHY
0xE80 TMR_FIPER1* - Timer fixed period interval R/W 0xFFFF_FFFF 16.5.3.10.13/16-119
0xE84 TMR_FIPER2* - Timer fixed period interval R/W 0xFFFF_FFFF
0xE88 TMR_FIPER*3 - Timer fixed period interval R/W 0xFFFF_FFFF
0xEA0 TMR_ETTS1_H* - Time stamp of general purpose external
trigger
R/W 0x0000_0000 16.5.3.10.14/16-120
0xEA4 TMR_ETTS1_L* - Time stamp of general purpose external trigger R/W 0x0000_0000
0xEA8 TMR_ETTS2_H* - Time stamp of general purpose external
trigger
R/W 0x0000_0000
0xEAC TMR_ETTS2_L* - Time stamp of general purpose external trigger R/W 0x0000_0000
0xEB0–
0xFFF
Reserved — — —
Other eTSECs
0x000–
0xFFF
eTSEC2 REGISTERS
4
1
Registers denoted * are new to the enhanced TSEC and not supported by PowerQUICC II Pro TSECs.
2
Key: R = read only, WO = write only, R/W = read and write, LH = latches high, SC = self-clearing.
3
Cleared on read.
4
eTSEC2 has the same memory-mapped registers that are described for eTSEC1 from 0x 2_4000 to 0x2_4FFF, except the
offsets are from 0x 2_5000 to 0x2_5FFF.
Table A-22. SerDes PHY Registers
SerDes PHY—Block Base Address 0xE_3000
Offset Register Access Reset Section/Page
0x000 SRDSCR0—SerDes Control Register 0 R/W 0x1100_CC30 15.3.1/15-4
0x004 SRDSCR1—SerDes Control Register 1 R/W 0x0000_0040 15.3.2/15-6
0x008 SRDSCR2—SerDes Control Register 2 R/W 0x0080_0000 15.3.3/15-7
0x00C SRDSCR3—SerDes Control Register 3 R/W 0x0101_0000 15.3.4/15-8
0x010 SRDSCR4—SerDes Control Register 4 R/W 0xnn00_0n0n 15.3.5/15-9
0x014–0x01C Reserved — — —
0x020 SRDSRSTCTL—SerDes Reset Control Register R/W 0x0044_4500 15.3.6/15-10
0x024–0x1FC Reserved — — —
Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers (continued)
eTSEC 1—Block Base Address 0x2_4000
eTSEC 2—Block Base Address 0x2_5000
eTSEC1
Offset
Name
1
Access
2
Reset Section/Page