Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor B-1
Appendix B
Revision History
This appendix provides a list of major differences between revisions of the MPC8308 PowerQUICC II Pro
Integrated Communications Processor Reference Manual.
Table B-1. Changes from Revision 0 to Revision 1
Section #
(Fig #/title
Table#/title)
Description
Throughout
Throughout Replaced signal name “RTC_PIT_CLK” with “RTC_PIT_CLOCK”.
Throughout Changed ‘USB_CLK_IN’ to ‘USBDR_CLK’.
Throughout Changed the bit name “LBIUCM” to “LBCM”.
About This Book
Section , “About This Book” Updated the “About This Book” topic.
Signal Descriptions
Tabl e 2-1, MPC8308 Signal
Reference by Functional Block
Figure 2-1, MPC8308 Signal
Groupings (1 of 2)
For the ‘CKSTOP_IN
’ signal, updated the alternate functions to ‘IRQ3/INTA.’
Throughout Removed TSEC2_TMR_Rx_ESFD, TSEC2_TMR_Tx_ESFD, TSEC1_TMR_Rx_ESFD
and TSEC1_TMR_Tx_ESFD signals.
Tabl e 2-1, MPC8308 Signal
Reference by Functional Block
Updated the description of the LBC_PM_REF_10 signal.
Reset, Clocking, and Initialization
Tabl e 4-19, Local Bus Controller
Setting When Loading RCW
For the ‘0000’ CFG_RESET_SOURCE, updated BR0[PS] from ‘11’ to ‘10.’
Section 4.4.1, “System Clock
Domains”
Changed LCCR[CLKDIV] to LCRR[CLKDIV].
Tabl e 4-19, Local Bus Controller
Setting When Loading RCW
Tabl e 4-20, RCW Values
Corresponding to Hard Coded
Options
Renamed the first column heading to “CFG_RESET_SOURCE[0:3]”.