Information
Revision History
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor B-3
Table 8-1, IPIC Signal Properties Added a row for the INTA signal.
Table 8-2, IPIC External
Signals—Detailed Signal
Descriptions
Added a row for the INTA signal.
Figure 8-16, System External
Interrupt Mask Register (SEMSR)
Removed the reset value footnote saying “The user should drive...”
DDR Memory Controller
Tabl e 9-3, Memory Interface
Signals—Detailed Signal
Descriptions
Updated the signal description of MA[13:0] from:
“Assertion/Negation—The address is always driven when the memory controller is
enabled. It is valid when a transaction is driven to DRAM (when MCS
n is active).”
to:
“Assertion/Negation—The address lines are only driven when the controller has a
command scheduled to issue on the address/CMD bus; otherwise they will be at high-Z.
It is valid when a transaction is driven to DRAM (when MCS
n is active).”
Enhanced Local Bus Controller
Section 10.4.4.4.7, “Address
Multiplexing (AMX)”
Added the section “Address Multiplexing (AMX)”.
Figure 10-64, RAM Word Fields
Table 10-40, RAM Word Field
Descriptions
Updated bits 26–27 from “Reserved” to “AMX”.
Table 10-38, Boot Bank Field Values
after Reset for FCM as Boot
Controller
Changed the setting for the “V” field from “0” to “1”.
Figure 10-35, GPCM General Write
Timing Parameters
Updated the figure.
Table 10-38, Boot Bank Field Values
after Reset for FCM as Boot
Controller
Changed the setting for the “DECC” field from “00” to “From LB_POR_CFG_BOOT_ECC”.
Table 10-2, Enhanced Local Bus
Controller Detailed Signal
Descriptions
Added a row for the “LBC_PM_REF_10” signal at the end of the table.
Section 10.1.2, “Features” Added the following bullet item at the end of the list:
“Different machines (FCM/GPCM/UPM) share the address, data, and control signals.
While the eLBC is servicing a transaction, subsequent transactions are queued until the
current transaction has completed.”
Table 10-23, LCRR Field
Descriptions
Updated the description of bit setting 1 of the LCRR[PBYP] bit as follows:
“The PLL is bypassed. (Default: This device supports PLL Bypass Mode only.)”
DMA Controller (DMAC)
Table B-1. Changes from Revision 0 to Revision 1
Section #
(Fig #/title
Table#/title)
Description