Information

Revision History
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
B-4 Freescale Semiconductor
Figure 12-17, TCD Word 2
(TCD.{smloe, dmloe, nbytes}) Field
Table 12-18, TCD Word 2
(TCD.{smloe, dmloe, nbytes})
Description
Updated the TCD Word 2 fields.
Universal Serial Bus Interface
Section 13.3.2.28, “USB General
Purpose Register
(CONTROL)—Non-EHCI”
Added the CONTROL[PHY_CLK_VALID] bit.
PCI Express Interface Controller
Table 14-3, PCI Express Memory
Map
Figure 14-79, PCI Express ACK
Replay Timeout Register
Updated the reset value of the PEX_ACKRPLY_TO register from 0x003B_2090 to
0x005B_2090.
Section 14.4.6.4, “PCI Express
Controller Core Clock Ratio Register
(PEX_GCLK_RATIO)”
In the first sentence, updated the maximum possible controller core frequency from ‘125
MHz’ to ‘133 MHz’.
Enhanced Three-Speed Ethernet Controllers
Table 16-40, MACCFG2 Field
Descriptions
In MACCFG2[I/F Mode] bitfield description, changed from "Reserved" to "1000 Mbps
RGMII" for bit setting “10”.
Table 16-1, eTSECn Network
Interface Signal Properties
Table 16-2, eTSEC
Signals—Detailed Signal
Descriptions
Removed TSECn_TMR_Rx_ESFD and TSECn_TMR_Tx_ESFD signals.
Section 16.5.3.10.1, “Timer Control
Register (TMR_CTRL)”
Made ESFDP and ESFDE signals ‘Reserved’.
Table 16-149, MII Interface Mode
Signal Configuration
For the MII Interface:
• Updated the frequency from ‘125’ to ‘25’
• Updated the voltage from ‘3.3/2.5’ to ‘3.3’
Table 16-125, RGMII and MII
Signals Multiplexing For the RGMII Interface, updated the voltage from ‘3.3/2.5’ to ‘2.5’.
Serial Peripheral Interface
Table B-1. Changes from Revision 0 to Revision 1
Section #
(Fig #/title
Table#/title)
Description