Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
4-18 Freescale Semiconductor
The device uses FCM to load the reset configuration from NAND Flash. The device reads 512 bytes if
small-page size NAND Flash is used or 2048 bytes if large-page NAND Flash is used. The local bus
controller’s registers setting are set according to Table 4-19.
4.3.3.2 Loading from I
2
C EEPROM
The device is capable of loading the reset configuration word from the I
2
C interface. If the device is
configured to load the reset configuration word from the I
2
C interface according to the reset configuration
input signals, the device uses the I
2
C unit boot sequencer in a special mode. In this mode, the I
2
C boot
sequencer is activated while the rest of the device is still in reset state (HRESET asserted) to load the reset
configuration words from an I
2
C serial EEPROM.
Note that this does not prevent using the I
2
C boot sequencer to initiate the device in the normal functional
mode after reset state has completed. The only restriction is that the first two EEPROM data structures
contain dedicated reset information.
4.3.3.2.1 Using the Boot Sequencer Reset Configuration
For more information on I
2
C interface and the boot sequencer, see Section 17.4.5, “Boot Sequencer
Mode.”
NOTE
When reset configuration words are loaded from an I
2
C EEPROM, an I
2
C
serial EEPROM of extended addressing type must be used.
If the I
2
C interface is used for loading the reset configuration words, the I
2
C module addresses the
EEPROM and reads the first two data structures (after reading the preamble). Upon being read, the reset
configuration words are latched inside the device and the I
2
C module enters its reset state until HRESET
is negated. There should be no other I
2
C traffic when the boot sequencer is active.
After HRESET is negated, the functional boot sequencer, in extended I
2
C addressing mode, may be
activated if the BOOTSEQ field of the reset configuration word high is set to 0b10.
4.3.3.2.2 EEPROM Calling Address
The device uses 0b101_0000 for the EEPROM calling address. The EEPROM to be addressed must
contain the reset configuration information and be programmed to respond to this address. No additional
EEPROMs are accessed by the boot sequencer in reset configuration mode.
Table 4-19. Local Bus Controller Setting When Loading RCW
CFG_RESET_SOURCE[0:3] Meaning BR0[PS] BR0[MSEL] OR0[SCY] OR0[PGS]
0000 NOR Flash 10 000 1111 NA
0001 NAND Flash, 8 bit,
small page
01 001 0010 0
0101 NAND Flash, 8 bit,
large page
01 001 0010 1