Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-10 Freescale Semiconductor
Table 5-11 defines the bit fields of PCIEXP1LAWBAR.
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5.1.4.6 PCI Express Local Access Window Attributes Registers
(PCIEXP1LAWAR)
The PCI Express 1 local access window attributes register is shown in Figure 5-7.
Table 5-12 defines the bit fields of PCIEXP1LAWAR.
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Table 5-11. PCIEXP1LAWBAR Bit Settings
Bits Name Description
0–19 BASE_ADDR Identifies the 20 most-significant address bits of the base of local access window. The specified base
address should be aligned to the window size, as defined by PCIEXP1LAWAR[SIZE].
20–31 — Reserved. Write has no effect, read returns 0.
Offset 0x84 Access: Read/Write
0 25 26 31
R
EN — SIZE
W
Reset All zeros
Figure 5-7. PCI Express 1 Local Access Window Attributes Register (PCIEXP1LAWAR)
Table 5-12. PCIEXP1LAWAR Bit Settings
Bits Name Description
0 EN 0 The PCI Express 1 local access window is disabled.
1 The PCI Express 1 local access window is enabled and other PCIEXP1LAWAR fields combine to identify
an address range for this window.
1–25 — Reserved. Write has no effect, read returns 0.
26–31 SIZE Identifies the size of the window from the starting address. Window size is 2
(SIZE+1)
bytes.
000000–001010 Reserved. Window is undefined.
001011 4 Kbytes
001100 8 Kbytes
001101 16 Kbytes
. . . . . . . 2
(SIZE+1)
bytes
011110 2 Gbytes
011111–111111 Reserved. Window is undefined.