Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-20 Freescale Semiconductor
Figure 5-14 shows SICRL.
Table 5-24 defines the bit fields of SICRL. Each Pin Function column lists the name of the multi-function
pin used in this option. Some groups have only two options (shown as Pin Function 0 and Pin Function 1)
and therefore, only one control bit. In this case they can only have a value of 0b0 or 0b1. Other groups may
have four options (shown as Pin Function 0, Pin Function 1, Pin Function 2, and Pin Function 3) and
therefore, two control bits. In this case they can have a value of 0b00, 0b01, 0b10, or 0b11. Use the
notations ‘0bN’ or ‘0bNN’ according to whether a group has one or two control bits, respectively.
Offset 0x00114 Access: Read/Write
01234567
R
Reserved SPI UART IRQ_B
W
Reset00000000
8 9 10 11 12 15
R
—I
2
C2 —
W
Reset00000000
16 23
R
—
W
Reset00000000
24 25 26 31
R
ETSEC1_A
1
—
W
Reset00000000
1
Bit #25 depends on the TSEC1M in the RCW. If it is set to RGMII, this bit is set to 1 on reset; for other values of
TSEC1M, this is zero.
Figure 5-14. System I/O Configuration Register Low (SICRL)
Table 5-25. SICRL Bit Settings
SICRL[Bits] Value 0b00 0b01 0b10 0b11
Reset
Bits Group Pin Function 0 Pin Function 1 Pin Function 2 Pin Function 3
0–1 — — — — — —
2–3 SPI
1
SPI_MOSI MSRCID4 — LSRCID4 00
SPI_MISO MDVAL — LDVAL
SPICLK — — —
SPISEL — — —