Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-25
24–26 — Reserved — — — —
27 TMROBI See Table 5 -27 for description and reset value.
28–29 — Reserved — — — —
30 TSOBI1
See Tabl e 5- 27 for description and reset value.
31 TSOBI2
1
When SICRH[eSDHC_A] = 0b01, SD_CLK and SD_CMD are in High-Z state.
2
Clock pulses may be observed on SD_CLK pin after reset until GPIO_16 is selected by setting SICRH[eSDHC_A]=0b11.
3
To enable the GPIO functionality, this bit must be programmed to 11.
Table 5-27. SICRH[27–31] Bit Settings
Bits Name Description Reset Value
23 GPIO_SEL GPIO[0:15] is provided at two places. This bit selects the position of the
GPIO registers.
0 Primary GPIO[0:15] provided as function-0, selectable through GPIO_A
and GPIO_B.
1 GPIO[0:15] provided in function-3, selectable through GTM,
IEEE1588_A, IEEE1588_B, and ETSEC2.
0
27 TMROBI
IEEE1588 timer TSEC_TMR ports output buffer impedance. This bit
controls the output buffer impedance of the TMR output/input signals used
for reduced pin mode interfaces (RGMII). The output buffer impedance
should be correlated to the voltage supplied to the TSEC1 I/O pins (LVDD1).
For non-eTSEC mode of operation, this bit must be cleared.
0 Output buffer is set for 40 , 3.3 V.
1 Output buffer is set for 40 , 2.5 V.
0
30 TSOBI1 TSEC1 output buffer impedance. This bit controls the output buffer
impedance of the TSEC1 output signals, used for reduced pin mode
interfaces (RGMII). The output buffer impedance should be correlated to the
voltage supplied to the TSEC1 I/O pins (LVDD1). For non-eTSEC mode of
operation, this bit must be cleared.
0 Output buffer is set for 40 , 3.3 V.
1 Output buffer is set for 40 , 2.5 V.
0 Else
1 RGMII
1
1
If RCWH[ETSEC1M] is RGMII, the reset value is 1; otherwise, it is 0
31 TSOBI2 TSEC2 output buffer impedance. This bit controls the output buffer
impedance of TSEC2 output signals, used for reduced pin mode interfaces
(RGMII). The output buffer impedance should be correlated to the voltage
supplied to the TSEC2 I/O pins (LVDD2).
0 Output buffer is set for 40 , 3.3 V.
1 Output buffer is set for 40 , 2.5 V.
0 Else
1 RGMII
2
Table 5-26. SICRH Bit Settings (continued)
SICRH[Bits] Value 0b00 0b01 0b10 0b11
Reset
Value
Bits Group Pin Function 0 Pin Function 1 Pin Function 2 Pin Function 3