Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-26 Freescale Semiconductor
5.2.2.7 Selection of Pin Functions During Reset
Few functions muxed with the I/Os are needed only during the period when the device is in reset state.
Those functionality are selected by default during the reset phase. Once the device comes out of reset, the
pad switches to the function needed for normal operation mode. The table below provides the list.
5.2.2.8 Debug Configuration
Debug information may be driven on the device pins. This information can identify the internal source of
a transaction that reached the DDR SDRAM or local bus interfaces. The device can be configured to drive
the MSRCID[0:4] and MDVAL or LSRCID[0:4] and LDVAL signals, respectively, on other device pins.
The coding of the source ID debug information is the same as the coding of the MSTR_ID field in the
AEATR register of the arbiter (See Section 6.2.7, “Arbiter Event Attributes Register (AEATR).”).
5.2.2.9 DDR Control Driver Register (DDRCDR)
The DDR control driver register (DDRCDR) contains bits that allow control over the driver of the DDR
SDRAM controller.
2
If RCWH[ETSEC2M] is RGMII, the reset value is 1; otherwise, it is 0.
NOTE
An empty column cannot be used for this register. A function should be
selected so that the column is non-empty.
Pin Name Function Selection during Reset
Normal Operation
Mode
TSEC1_TX_ER LB_POR_CFG_BOOT_ECC TSEC1_TX_ER
TSEC1_TXD3 CFG_RESET_SOURCE[0] TSEC1_TXD3
TSEC1_TXD2 CFG_RESET_SOURCE[1] TSEC1_TXD2
TSEC1_TXD1 CFG_RESET_SOURCE[2] TSEC1_TXD1
TSEC1_TXD0 CFG_RESET_SOURCE[3] TSEC1_TXD0
TSEC1_TX_EN LBC_PM_REF_10 TSEC1_TX_EN