Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-36 Freescale Semiconductor
Table 5-35 defines the bit fields of SWCNR.
5.3.4.3 System Watchdog Service Register (SWSRR)
The system watchdog service register (SWSRR) is shown in Figure 5-24. When the watchdog timer is
enabled, a write of 0x556C followed by a write 0xAA39 to the SWSRR register before the watchdog
counter times out prevents a device reset. If the SWSRR register is not serviced before the timeout, a signal
from the watchdog timer to the reset or interrupt controller module asserts a system reset or interrupt
(depending on the setting of SWCRR[SWRI]).
Both writes must occur before the timeout in the order listed, but any number of instructions can be
executed between the two writes. However, writing any value other than 0x556C or 0xAA39 to the
SWSRR register resets the servicing sequence, requiring both values to be written to keep the watchdog
timer from causing a reset. Reset initializes the SWSRR[WS] field to 0x0000. SWSRR can be written at
any time, but returns all zeros when read.
Table 5-36 defines the bit fields of SWCNR.
Table 5-35. SWCNR Bit Settings
Bits Name Description
0–15 — Write reserved, read = 0
16–31 SWCN Software watchdog count field. The read-only SWCNR[SWCN] field reflects the current value in the watchdog
counter. Writing to the SWCNR register has no effect, and write cycles are terminated normally. Reset
initializes the SWCNR[SWCN] field to 0xFFFF.
Note: Reading the 16 least-significant bits of 32-bit SWCNR register with two 8-bit reads is not guaranteed
to return a coherent value.
Offset 0xE Access: Write only
0 15
R
WWS
Reset All zeros
Figure 5-24. System Watchdog Service Register (SWSRR)
Table 5-36. SWSRR Bit Settings
Bits Name Description
0–15 WS Software watchdog service field.
The user should periodically write 0x556C followed by 0xAA39 to this register to prevent a software watchdog
timer timeout. SWSRR[WS] can be written at any time, but returns all zeros when read.