Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 5-37
5.3.5 Functional Description
This section provides a functional description of the software watchdog timer (WDT) unit, including a
state diagram, block diagram, and discussion of modes of operation.
5.3.5.1 Software Watchdog Timer Unit
The device provides a software watchdog timer feature to prevent system lock in case the software
becomes trapped in loops with no controlled exit. Watchdog timer operations are configured in the system
watchdog control register (SWCRR).
The software watchdog timer is enabled after reset to cause a soft reset or non-maskable interrupt (MCP)
if it times out. If the software watchdog timer is not needed, the user must clear SWCRR[SWEN] to disable
it. If used, the software watchdog timer requires a special service sequence to be executed periodically.
Without this periodic servicing, the software watchdog timer times out and issues a reset or a nonmaskable
interrupt, as programmed in SWCRR[SWRI]. Once software writes SWRI, the state of SWEN cannot be
changed.
The software watchdog timer service sequence consists of the following two steps:
• Write 0x556C to the system watchdog service register (SWSRR)
• Write 0xAA39 to SWSRR
The service sequence reloads the watchdog timer and the timing process begins again. If a value other than
0x556C or 0xAA39 is written to the SWSRR, the entire sequence must start over. Although the writes must
occur in the correct order before a time-out, any number of instructions can be executed between the
writes. This allows interrupts and exceptions to occur between the two writes when necessary. Figure 5-25
shows a state diagram for the watchdog timer.
Figure 5-25. Software Watchdog Timer Service State Diagram
0x556C/Do Not Reload
Reset
0xAA39/Reload
State 0
Waiting for 0x556C
State 1
Waiting for 0xAA39
Not 0xAA39/Do Not Reload
Not 0x556C/Do Not Reload