Information

System Configuration
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
5-42 Freescale Semiconductor
5.4.6.1 Real Time Counter Control Register (RTCNR)
The real time counter control register (RTCNR), shown in Figure 5-28, is used to enable RTC functions.
The register can be read at any time.
Table 5-39 lists the bit fields of RTCNR.
Offset 0x00 Access: Read/Write
0 23 24 25 26 29 30 31
R
— CLEN CLIN — AIM SIM
W
Reset All zeros
Figure 5-28. Real Time Counter Control Register (RTCNR)
Table 5-39. RTCNR Bit Settings
Bits Name Description
0–23 — Write reserved, read = 0
24 CLEN Clock enable control bit.
This bit controls the counting of the RTC. When the RTC’s clock is disabled, the counter maintains its old
value. When the counter’s clock is enabled, it continues counting using the previous value.
0 Disable counter.
1 Enable counter.
25 CLIN Input clock control bit.
The input clock to the RTC may be either the CSB clock or an external RTC clock.
0 The input clock to the RTC is CSB input clock.
1 The input clock to the RTC is the external RTC clock. If RTC-standby operation is required, this bit should
be set to 1.
26–29 — Write reserved, read = 0
30 AIM Alarm interrupt mask bit.
Used to enable or disable (mask) the RTC alarm interrupt when the RTC’s 32-bit counter reaches
RTALR[ALR] value.
0 Alarm interrupt generation disabled.
1 Alarm interrupt generation enabled.
31 SIM Second interrupt mask bit.
Used to enable or disable (mask) the RTC periodic interrupt.
0 Periodic interrupt generation disabled.
1 Periodic interrupt generation enabled.