Information

Arbiter and Bus Monitor
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 6-9
6.2.7 Arbiter Event Attributes Register (AEATR)
The arbiter event attributes register (AEATR) reports the type of transaction that causes error that is
specified in the event register. See Section 6.2.4, “Arbiter Event Register (AER),” for more information.
AEATR is cleared only by power-on reset. The attributes of the first error event are stored. Note that this
means that AEATR does not change its value when AER is not clear. As AEATR is not affected by soft or
hard reset, software can read this register and determine the cause of the bus failure, even if the failure
caused a deadlock situation. For more information, see Section 6.4.2, “Error Handling Sequence.”
Figure 6-7 shows the fields of AEATR.
Table 6-8 describes AEATR fields.
30 DTO Data time out. Data tenure time out interrupt mask bit.
0 Data tenure time out interrupt disabled.
1 Data tenure time out interrupt enabled.
31 ATO Address time out. Address tenure time out interrupt mask bit.
0 Address tenure time out interrupt disabled.
1 Address tenure time out interrupt enabled.
Offset 0x18 Access: Read only
0 4 5 7 8 1011 1516 19 20 21 2324 2627 31
R
— EVENT — MSTR_ID — TBST TSIZE — TTYPE
W
Reset All zeros
Figure 6-7. Arbiter Event Attributes Register (AEATR)
Table 6-8. AEATR Field Descriptions
Bits Name Description
0–4 — Write reserved, read = 0
5–7 EVENT Event type.
000 Address time out
001 Data time out
010 Address only transfer type
011 External control word transfer type
100 Reserved transfer type
101 Transfer error
11c Reserved
8–10 — Write reserved, read = 0
Table 6-7. AMR Field Descriptions (continued)
Bits Name Description