Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 7-1
Chapter 7
e300 Processor Core Overview
This chapter provides an overview of features for the embedded microprocessors in the e300 core family,
which are PowerPC microprocessors built on Power Architecture technology. Throughout this chapter, the
terms ‘e300 core’, ‘core’, and ‘processor’ are used interchangeably. The term, ’e300c3’ is used when
describing an implementation-specific feature or when a difference exists between different
configurations. The term ‘e300’ is used when describing a feature that pertains to the family of e300
processors. The MPC8308 uses an e300c3 core.
7.1 Overview
This section describes the details of the e300 core, provides a block diagram showing the major functional
units, and briefly describes how these units interact. For additional information, see e300 Power
Architecture™ Core Family Reference Manual.
The e300 core is a low-power implementation of this microprocessor family of reduced instruction set
computing (RISC) microprocessors. The core implements the 32-bit portion of the PowerPC architecture,
which defines 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data
types of 32 and 64 bits.
The core is a superscalar processor that can issue and retire as many as three instructions per clock cycle.
Instructions can execute out of program order for increased performance; however, the core makes
completion appear sequential.
The e300 core integrates independent execution units including: an integer unit (IU), a floating-point unit
(FPU), a branch processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The
e300c3 integrates an additional integer unit for a total of two IUs. The ability to execute instructions in
parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput
for e300 core-based systems. Most integer instructions execute in one-clock cycle. The additional IUs
along with enhanced multipliers in the e300c3 improve multiply instructions to a maximum two-cycle
latency, a significant improvement from previous processors. In the e300c3 core, the FPU is pipelined so
a single-precision multiply-add instruction can be issued and completed every clock cycle. The e300c3
core provide hardware support for all single- and double-precision floating-point operations for most value
representations and all rounding modes.