Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
7-14 Freescale Semiconductor
7.4 Implementation-Specific Information
This section describes the PowerPC architecture in general and specific details about the implementation
of the e300 core as a low-power, 32-bit member of this PowerPC core family. The main topics addressed
are as follows:
• Section 7.4.1, “Register Model,” describes the registers for the operating environment architecture
common among e300 cores that implement the PowerPC architecture and describes the
programming model. It also describes the additional registers that are unique to the core.
• Section 7.4.2, “Instruction Set and Addressing Modes,” describes the PowerPC instruction set and
addressing modes for the OEA, and defines and describes the instructions implemented in the core.
• Section 7.4.3, “Cache Implementation,” describes the cache model that is defined generally for
cores that implement the PowerPC architecture by the VEA. It also provides specific details about
the e300 core cache implementation.
• Section 7.4.4, “Interrupt Model,” describes the interrupt model of the OEA and the differences in
the core interrupt model.
• Section 7.4.5, “Memory Management,” describes generally the conventions for memory
management among these cores. This section also describes the core implementation of the 32-bit
PowerPC memory management specification.
• Section 7.4.6, “Instruction Timing,” provides a general description of the instruction timing
provided by the superscalar, parallel execution supported by the PowerPC architecture and the
e300 core.
• Section 7.1.6, “Bus Interface Unit (BIU),” describes the signals implemented on the core.
The e300 core is a high-performance, superscalar processor core. The PowerPC architecture allows
optimizing compilers to schedule instructions to maximize performance through efficient use of the
PowerPC instruction set and register model. The multiple, independent execution units allow compilers to
optimize instruction throughput. Compilers that take advantage of the flexibility of the PowerPC
architecture can additionally optimize system performance.
The following sections summarize the features of the core, including both those that are defined by the
architecture and those that are unique to the various core implementations.
Specific features of the core are listed in Section 7.1.1, “Features.”
7.4.1 Register Model
The PowerPC architecture defines register-to-register operations for most computational instructions.
Source operands for these instructions are accessed from the registers or are provided as immediate values
embedded in the instruction opcode. The three-register instruction format allows specification of a target
register distinct from the two-source operands. Load and store instructions transfer data between registers
and memory.
The e300 core has two levels of privilege: supervisor mode of operation (typically used by the operating
system) and user mode of operation (used by the application software). The programming models
incorporate 32 GPRs, 32 FPRs, special-purpose registers (SPRs), and several miscellaneous registers.
Each core also has its own unique set of hardware implementation (HID) registers.