Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 7-19
16 EE External interrupt enable
0 The processor ignores external interrupts, system management interrupts, and decrementer interrupts.
1 The processor is enabled to take an external interrupt, system management interrupt, or decrementer
interrupt.
17 PR Privilege level
0 The processor can execute both user- and supervisor-level instructions
1 The processor can only execute user-level instructions
18 FP Floating-point available
0 The processor prevents dispatch of floating-point instructions, including floating-point loads, stores, and
moves.
1 The processor can execute floating-point instructions and can take floating-point enabled exception type
program interrupts.
19 ME Machine check enable
0 Machine check interrupts are disabled
1 Machine check interrupts are enabled
20 FE0 Floating-point exception mode 0
21 SE Single-step trace enable
0 The processor executes instructions normally
1 The processor generates a trace interrupt upon the successful completion of the next instruction
22 BE Branch trace enable
0 The processor executes branch instructions normally
1 The processor generates a trace interrupt upon the successful completion of a branch instruction
23 FE1 Floating-point exception mode 1
24 CE Critical interrupt enable
0 Critical interrupts disabled
1 Critical interrupts enabled; critical interrupt and rfci instruction enabled
The critical interrupt is an asynchronous implementation-specific interrupt. The critical interrupt vector offset
is 0x00A00. The rfci instruction is implemented to return from these interrupt handlers. Also, CSRR0 and
CSRR1 are used to save and restore the processor state for critical interrupts.
25 IP Interrupt prefix. The setting of this bit specifies whether an interrupt vector offset is prepended with Fs or 0s.
In the following description, nnnnn is the offset of the interrupt.
0 Interrupts are vectored to the physical address 0x000n_nnnn
1 Interrupts are vectored to the physical address 0xFFFn_nnnn
26 IR Instruction address translation
0 Instruction address translation is disabled
1 Instruction address translation is enabled
27 DR Data address translation
0 Data address translation is disabled
1 Data address translation is enabled
28 — Reserved. Full function.
29 PMM Performance monitor mark bit (e300c3 ). System software can set PMM when a marked process is running to
enable statistics to be gathered only during the execution of the marked process. MSR[PR] and MSR[PMM]
together define a state that the processor (supervisor or user) and the process (marked or unmarked) may be
in at any time. If this state matches an individual state specified in the PMLCan, the state for which monitoring
is enabled, counting is enabled.
Table 7-2. MSR Bit Descriptions (continued)
Bits Name Description