Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
7-20 Freescale Semiconductor
7.4.1.3.2 Segment Registers (SRs)
For memory management, 32-bit processors implement sixteen 32-bit SRs. To speed access, the core
implements the SRs as two arrays: a main array for data memory accesses and a shadow array for
instruction memory accesses. Loading a segment entry with the Move to Segment Register (mtsr)
instruction loads both arrays.
7.4.1.3.3 Supervisor-Level SPRs
The e300 core, like the G2_LE core, has additional supervisor-level SPRs, which are shown in Figure 7-3.
Two critical interrupt SPRs (CSRR0 and CSRR1), eight SPRGs (SPRG0–SPRG7), eight pairs of
instruction BATs (IBAT0–IBAT7), eight pairs of data BATs (DBAT0–DBAT7), one system version
register (SVR), one system memory base address (MBAR), one instruction address breakpoint control
(IBCR), one data address breakpoint control (DBCR), a new instruction breakpoint register (IABR2), and
two data address breakpoint registers (DABR and DABR2) are integrated into the core.
The following list discusses the supervisor-level SPRs.
• The DSISR defines the cause of data access and alignment interrupts. The cause of a DSI interrupt
for a data breakpoint (match with DABR and DABR2) can be determined by the value of the
DSISR[DABR] bit (bit 9).
• The data address register (DAR) holds the address of an access after an alignment or DSI interrupt.
For example, it contains the address of the breakpoint match condition.
• The decrementer register (DEC) is a 32-bit decrementing counter that provides a mechanism for
causing a decrementer interrupt after a programmable delay.
• SDR1 specifies the page table format used in virtual-to-physical address translation for pages.
(Note that physical address is referred to as ‘real address’ in the architecture specification.)
• The machine status save/restore register 0 (SRR0) is used for saving the address of the instruction
that caused the interrupt, and the address to return to when a Return from Interrupt (rfi) instruction
is executed.
• The machine status save/restore register 1 (SRR1) is used to save machine status on interrupts and
to restore machine status when an rfi instruction is executed.
• The SPRG0–SPRG7 registers are provided for operating system use. They reduce the latency that
may be incurred in the saving of registers to memory while in a handler. Note that the e300
implements four more SPRGs than the G2 (SPRG0–SPRG3).
30 RI Recoverable interrupt (for system reset and machine check interrupts)
0 Interrupt is not recoverable
1 Interrupt is recoverable
31 LE Little-endian mode enable
0 The processor runs in big-endian mode
1 The processor runs in little-endian mode.
1
All reserved bits should be set to zero for future compatibility.
Table 7-2. MSR Bit Descriptions (continued)
Bits Name Description