Information

e300 Processor Core Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 7-21
• The time base register (TB) is a 64-bit register that maintains the time of day and operates interval
timers. It consists of two 32-bit fields: time base upper (TBU) and time base lower (TBL).
• The processor version register (PVR) is a read-only register that identifies the version (model) and
revision level of the processor. See Table 7-9 for the version and revision level of the PVR for the
e300 processor core.
• The PowerPC architecture defines 16 block address translation (BAT) registers. The e300 core
includes a total of eight pairs of DBAT and eight pairs of IBAT registers. See Figure 7-2 for a list
of the SPR numbers for the BAT arrays.
The following supervisor-level SPRs are implementation-specific (not defined in the PowerPC
architecture):
• DMISS and IMISS are read-only registers that are loaded automatically on an instruction or data
TLB miss.
• HASH1 and HASH2 contain the physical addresses of the primary and secondary page table entry
groups (PTEGs).
• ICMP and DCMP contain a duplicate of the first word in the page table entry (PTE) for which the
table search is looking.
• The required physical address (RPA) register is loaded by the core with the second word of the
correct PTE during a page table search.
• The system version register (SVR) is available on the e300 core, which identifies the specific
version (model) and revision level of the system-on-a-chip (SOC) integration.
• System memory base address (MBAR) is an implementation-specific register available on the
e300 core. It supports a temporary storage for the system-level memory map.
• The instruction and data address breakpoint registers (IABR, IABR2, DABR, and DABR2) are
loaded with an instruction or data address, respectively, that is compared to instruction addresses
in the dispatch queue or to the data address in the LSU. When an address match occurs, a
breakpoint interrupt is generated.
• One instruction breakpoint control register (IBCR) and one data breakpoint control register
(DBCR) are implemented in the e300 core.
• To support critical interrupts, two registers (CSRR0 and CSRR1) are included in the e300 core.
• Eight SPRG registers (SPRG0–SPRG7) are in the e300 core.
• Block address translation (BAT) arrays—The e300 core has eight instruction and eight data BAT
registers.
• The hardware implementation (HID0 and HID1) registers provide the means for enabling core
checkstops and features and allow software to read the configuration of the PLL configuration
signals. The HID2 register enables the true little-endian mode, cache way-locking, and the
additional BAT registers.