Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 8-19
Note that in core disabled mode the user should use the int output interrupt type (should not use cint or smi
output interrupt types) to read an updated SIVCR.
Table 8-17 defines the bit fields of SICNR.
Offset 0x28 Access: Read write
01234 789101112 151617181920 232425262728 31
R
SYSD0T SYSD1T — SYSC0T SYSC1T — SYSB0T SYSB1T — SYSA0T SYSA1T —
W
Reset All zeros
Figure 8-12. System Internal Interrupt Control Register (SICNR)
Table 8-17. SICNR Field Descriptions
Bits Name Description
0–1 SYSD0T SYSD0 priority position IPIC output interrupt type. Defines which type of the IPIC output interrupt signal (int
,
cint, or smi) asserts its request to the core in the SYSD0 priority position. These bits cannot be changed
dynamically. (to change it, software must make sure the corresponding interrupt source is masked or it cannot
happen during the change).
The definition of SYSD0T is as follows:
00 int
request is asserted to the core for SYSD0.
01 smi
request is asserted to the core for SYSD0.
10 cint request is asserted to the core for SYSD0.
11 Reserved
2–3 SYSD1T Same as SYSD0T, but for SYSD1T.
4–7 — Write ignored, read = 0
8–9 SYSC0T SYSC0 priority position IPIC output interrupt Type. Defines which type of the IPIC output interrupt signal (int,
cint
, or smi) asserts its request to the core in the SYSC0 priority position. These bits cannot be changed
dynamically. (If s/w really wants to change it, it has to make sure the corresponding interrupt source is masked
or it won’t happen during the change).
The definition of SYSC0T is as follows:
00 int
request is asserted to the core for SYSC0.
01 smi request is asserted to the core for SYSC0.
10 cint
request is asserted to the core for SYSC0.
11 Reserved
10–11 SYSC1T Same as SYSC0T, but for SYSC1T.
12–15 — Write ignored, read = 0
16–17 SYSB0T SYSB0 priority position IPIC output interrupt Type. Defines which type of the IPIC output interrupt signal (int,
cint
, or smi) asserts its request to the core in the SYSB0 priority position. These bits cannot be changed
dynamically. (If software really wants to change it, it has to make sure the corresponding interrupt source is
masked or it does not happen during the change).
The definition of SYSB0T is as follows:
00 int
request is asserted to the core for SYSB0.
01 smi request is asserted to the core for SYSB0.
10 cint
request is asserted to the core for SYSB0.
11 Reserved
18–19 SYSB1T Same as SYSB0T, but for SYSB1T.
20–23 — Write ignored, read = 0