Information

Integrated Programmable Interrupt Controller (IPIC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
8-30 Freescale Semiconductor
Table 8-31 defines the bit fields of SERFR.
8.5.22 System Critical Interrupt Vector Register (SCVCR)
SCVCR, shown in Figure 8-26, contains a 7-bit code (Table 8-32) representing the unmasked critical
interrupt (cint) source of the highest priority level.
Note that in core-disabled mode the user should use SIVCR only to read an updated interrupt vector
(SCVCR should not be used).
Table 8-32 defines SCVCR bit fields.
8.5.23 System Management Interrupt Vector Register (SMVCR)
SMVCR, shown in Figure 8-27, contains a 7-bit code (Table 8-33) representing the unmasked system
management interrupt (smi) source of the highest priority level.
Table 8-31. SERFR Field Descriptions
Bits Name Description
0–31 INTn Each implemented bit, listed in Ta ble 8 -2 3, corresponds to an external MCP source. The user forces an MCP by
setting the SERFR bit.
SERFR bit positions are not affected by their relative priority.
Attempts to write to unimplemented (reserved) bits are ignored; read = 0
Offset 0x60 Access: Read only
056 24 25 31
R CVECx
—
CVEC
W
Reset All zeros
Figure 8-26. System Critical Interrupt Vector Register (SCVCR)
Table 8-32. SCVCR Field Descriptions
Bits Name Description
0–5 CVECx Backward (MPC8260) compatible critical interrupt vector. Specifies a 6-bit unique number of the IPIC’s
highest priority critical interrupt source, pending to the core. When a critical interrupt request occurs, SCVCR
can be read. If there are multiple critical interrupt sources, SCVCR latches the highest priority critical
interrupt. Note that CVECx field will correctly reflect only first 64 interrupt vectors (See Tabl e 8-6 for details).
The value of SCVEC cannot change while it is being read.
6–24 — Write ignored, read = 0
25–31 CVEC Critical interrupt vector. Specifies a 7-bit unique number of the IPIC’s highest priority critical interrupt source,
pending to the core. When a critical interrupt request occurs, SCVCR can be read. If there are multiple critical
interrupt sources, SCVCR latches the highest priority critical interrupt. Note that CVEC field correctly reflects
all of the interrupt vectors (See Table 8-6 for details).
The value of SCVEC cannot change while it is being read.