Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 9-3
— Unbuffered and registered DIMMs
• Chip select interleaving support
• Support for data mask signals and read-modify-write for sub-double-word writes. Note that a
read-modify-write sequence is only necessary when ECC is enabled.
• Support for double-bit error detection and single-bit error correction ECC (8-bit check word across
64-bit data)
• Open page management (dedicated entry for each logical bank)
• Automatic DRAM initialization sequence or software-controlled initialization sequence
• Automatic DRAM data initialization
• Support for up to eight posted refreshes
• Memory controller clock frequency of two times the SDRAM clock with support for sleep power
management
• Support for error injection
9.2.1 Modes of Operation
The DDR memory controller supports the following modes:
• Dynamic power management mode. The DDR memory controller can reduce power consumption
by negating the SDRAM CKE signal when no transactions are pending to the SDRAM.
• Auto-precharge mode. Clearing DDR_SDRAM_INTERVAL[BSTOPRE] causes the memory
controller to issue an auto-precharge command with every read or write transaction.
Auto-precharge mode can be enabled for separate chip selects by setting
CSn_CONFIG[AP_n_EN].
9.3 External Signal Descriptions
This section provides descriptions of the DDR memory controller’s external signals. It describes each
signal’s behavior when the signal is asserted or negated and when the signal is an input or an output.
9.3.1 Signals Overview
Memory controller signals are grouped as follows:
• Memory interface signals
• Clock signals
• Debug signals