Information

DDR Memory Controller
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
9-10 Freescale Semiconductor
9.4.1 Register Descriptions
This section describes the DDR memory controller registers. Shading indicates reserved fields that should
not be written.
9.4.1.1 Chip Select Memory Bounds (CSn_BNDS)
The chip select bounds registers (CSn_BNDS) define the starting and ending address of the memory space
that corresponds to the individual chip selects. Note that the size specified in CSn_BNDS should equal the
size of physical DRAM. Also, note that EAn must be greater than or equal to SAn.
0x110 DDR_SDRAM_CFG—DDR SDRAM control configuration R/W 0x0200_0000 9.4.1.7/9-19
0x114 DDR_SDRAM_CFG_2—DDR SDRAM control configuration 2 R/W 0x0000_0000 9.4.1.8/9-22
0x118 DDR_SDRAM_MODE—DDR SDRAM mode configuration R/W 0x0000_0000 9.4.1.9/9-23
0x11C DDR_SDRAM_MODE_2—DDR SDRAM mode configuration 2 R/W 0x0000_0000 9.4.1.10/9-24
0x120 DDR_SDRAM_MD_CNTL—DDR SDRAM mode control R/W 0x0000_0000 9.4.1.11/9-25
0x124 DDR_SDRAM_INTERVAL—DDR SDRAM interval configuration R/W 0x0000_0000 9.4.1.12/9-27
0x128 DDR_DATA_INIT—DDR SDRAM data initialization R/W 0x0000_0000 9.4.1.13/9-28
0x130 DDR_SDRAM_CLK_CNTL—DDR SDRAM clock control R/W 0x0200_0000 9.4.1.14/9-28
0x140–
0x144
Reserved — — —
0x148 DDR_INIT_ADDR—DDR training initialization address R/W 0x0000_0000 9.4.1.15/9-29
0x150–
0xBF4
Reserved — — —
0xBF8 DDR_IP_REV1—DDR IP block revision 1 R 0xnnnn_nnnn
1
9.4.1.16/9-29
0xBFC DDR_IP_REV2—DDR IP block revision 2 R 0x00nn_00nn
1
9.4.1.17/9-30
0xE00 DATA_ERR_INJECT_HI—Memory data path error injection mask high R/W 0x0000_0000 9.4.1.18/9-30
0xE04 DATA_ERR_INJECT_LO—Memory data path error injection mask low R/W 0x0000_0000 9.4.1.19/9-31
0xE08 ERR_INJECT—Memory data path error injection mask ECC R/W 0x0000_0000 9.4.1.20/9-31
0xE20 CAPTURE_DATA_HI—Memory data path read capture high R/W 0x0000_0000 9.4.1.21/9-32
0xE24 CAPTURE_DATA_LO—Memory data path read capture low R/W 0x0000_0000 9.4.1.22/9-32
0xE28 CAPTURE_ECC—Memory data path read capture ECC R/W 0x0000_0000 9.4.1.23/9-33
0xE40 ERR_DETECT—Memory error detect w1c 0x0000_0000 9.4.1.24/9-33
0xE44 ERR_DISABLE—Memory error disable R/W 0x0000_0000 9.4.1.25/9-34
0xE48 ERR_INT_EN—Memory error interrupt enable R/W 0x0000_0000 9.4.1.26/9-35
0xE4C CAPTURE_ATTRIBUTES—Memory error attributes capture R/W 0x0000_0000 9.4.1.27/9-36
0xE50 CAPTURE_ADDRESS—Memory error address capture R/W 0x0000_0000 9.4.1.28/9-37
0xE54 Reserved — — —
0xE58 ERR_SBE—Single-Bit ECC memory error management R/W 0x0000_0000 9.4.1.29/9-37
1
Implementation-dependent reset values are listed in specified section/page.
Table 9-5. DDR Memory Controller Memory Map (continued)
Offset Register Access Reset Section/Page